ParTec AG announces major participation in advancing Europe’s Digital Autonomy in HPC and AI with the DARE SGA1 Project

ParTec AG announces major participation in advancing Europe’s Digital Autonomy in HPC and AI with the DARE SGA1 Project

Munich, April 9, 2025 – ParTec AG (ISIN: DE000A3E5A34 / WKN: A3E5A3) is proud to announce its pivotal role in the groundbreaking "Digital Autonomy with RISC-V in Europe, Special Grant Agreement 1 project (DARE SGA1). As a large-scale European initiative, DARE SGA1 aims to strengthen Europe’s technological independence in High-Performance Computing (HPC) and Artificial Intelligence (AI). Supported by the EuroHPC Joint Undertaking and coordinated by the Barcelona Supercomputing Center (BSC-CNS), the project unites 38 leading partners from across Europe to develop the next generation of European processors and computing systems. This initiative also includes building an optimized software ecosystem for both scientific and industrial applications. Within the consortium, ParTec AG has a key role with several contributions to the project continuing to leverage its expertise pioneering the dynamic Modular System Architecture (dMSA) in Europe.

Integration and prototyping

ParTec plays a central role in the technical area of "Integration and Prototyping" within the DARE SGA1 project, focusing on two main aspects:

1. System Design of the DARE Prototype: ParTec contributes to designing a prototype system that integrates RISC-V based general-purpose server CPU, an AI inference accelerator, and a CPU specialized for long vector processing. This innovative design enables high processing efficiency and performance.
2. Creation of a Digital Twin: ParTec is collaborating with IMEC developing a digital twin for large supercomputers to predict performance and energy consumption of the developed prototype in large-scale HPC/AI setups. ParTec’s focus is on modelling the communication behaviour between nodes to optimize system integration.

These advancements will demonstrate the practical benefits of RISC-V-based processors for HPC and AI applications and enable accurate performance predictions for large-scale configurations. Additionally, the work will support future projects within the DARE framework to develop cutting-edge RISC-V processors and systems.

Shared applications and software

As a leader in the technical area of "Shared Applications and Software," ParTec also drives innovation with respect to these efficiency topics.

1. Resource Management and Energy Efficiency: ParTec leads the work done in this area and adapts its ParaStation MPI Resource Management to the DARE platform, optimizing resource allocation for enhanced performance.
2. Optimizing the ParaStation MPI Runtime Library: ParTec fine-tunes the library for both vector and general-purpose CPUs, ensuring efficient execution on the heterogeneous prototype system developed by DARE SGA1.

By advancing these capabilities, ParTec enables near-optimal execution of distributed memory applications on the RISC-V-based systems, laying the groundwork for future enhancements.

For Bernhard Frohwitter, CEO ParTec AG, the participation in the project is a proof for the company’s expertise and industry recognition: “We are proud to be part of the DARE SGA1 project. It is an exciting opportunity to show the advantages of RISC-V-based processors for high-performance computing and AI applications. This work will help us predict how these processors perform at scale and lay the groundwork for co-designing future RISC-V systems within the DARE framework. In addition, our expertise in resource management and energy efficiency will enable near-optimal execution of distributed-memory applications on heterogeneous RISC-V based systems developed by DARE SGA1 and later projects.”

About DARE

Digital Autonomy with RISC-V in Europe (DARE SGA1) is a large-scale European supercomputing project that has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 101202459.

DARE SGA1 aims to develop prototype HPC and AI systems based on EU-designed and developed industry-standard chiplets, using the latest silicon technology nodes to achieve the highest performance and energy efficiency. This three-year, 38 partner initiative, with a budget of €240 million and coordinated by Barcelona Supercomputing Center (BSC-CNS), will develop a comprehensive supercomputing compute stack, featuring high-performance and energy-efficient processors designed and developed in Europe, enabled by an optimized software stack.

For more information about DARE SGA1 and its progress, visit DARE website or contact dare_dissemination@bsc.es .

About ParTec AG

ParTec AG specialises in the development and manufacture of AI supercomputers based on its modular High-Performance Computing (HPC) systems and Quantum Computers (QC) as well as the associated system software. The offering also includes consulting and support services in all areas of the development, construction, and operation of these modern systems. The concept of dynamic Modular System Architecture (dMSA) is the result of more than fifteen years of research and was developed by ParTec as a novel system design for massively parallel high computing systems. The dMSA and the underlying ParaStation Modulo Software Suite, which has been developed and is maintained by ParTec, have proven to be particularly suitable for the complex requirements of massive computing power in Artificial Intelligence (AI).

Further information about the company and ParTec AG’s innovative solutions in the field of high-performance computing and quantum computing can be found at www.par-tec.com.

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Dieter Niewierra
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E-Mail: press@par-tec.com

Phone: +49 151 160 444 70

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Anna Lehmann
E-Mail: investor-relations@par-tec.com

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Doron Kaufmann

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Phone: +49 69 905 505 51